This invention relates generally to output driver circuits for driving the inputs of an output stage, and more particularly to those output driver circuits capable of driving the inputs of an all N-channel output stage with a boosted voltage.
Two types of field-effect transistor ("FET") output stages are shown in FIGS. 1A and 1B. Referring to FIG. 1A, output stage 20 has two N-channel transistors 22 and 24. Transistor 22 is normally referred to as a "pullup" transistor, and transistor 24 is normally referred to as a "pulldown" transistor. The gates of transistors 22 and 24 form first and second inputs 23 and 25. The drain of transistor 22 is coupled to a supply voltage VCC, typically five volts, at terminal 21. The source of transistor 24 is coupled to a negative supply voltage or ground at terminal 28. The source of transistor 22 and the drain of transistor 24 are coupled together to form an output 32.
In a normal mode of operation, the first and second inputs 23 and 25 are complementary and are therefore driven differentially. To produce a logic low voltage at output 32, input 23 is coupled to a logic low voltage and input 25 is coupled to a logic high voltage. Thus, transistor 22 is biased off and transistor 24 is biased on, effectively shorting output 32 to ground through the low drain-to-source resistance of transistor 24 and isolating output 32 from the supply voltage through the high drain-to-source resistance of transistor 24. To produce a logic high voltage at output 32, the polarities of the signals at inputs 23 and 25 are inverted. In a high impedance or "tristate" output mode, inputs 23 and 25 can also both be held low to turn off both transistors 22 and 24.
Referring to FIG. 1B, output stage 20A has a P-channel pullup transistor 22A and an N-channel pulldown transistor 24. As output state 20, the gates of transistors 22 and 24 form first and second inputs 23 and 25. The source of transistor 22 is coupled to the supply voltage VCC at terminal 21 and the source of transistor 24 is coupled to ground at terminal 28. The drains of transistors 22 and 24 are coupled together to form the output 32.
In a normal mode of operation, the first and second inputs 23 and 25 require the same polarity to switch the output 32. Therefore, inputs 23 and 25 can be coupled together to the same logic input signal. However, if a tristate output feature is desired, inputs 23 and 25 can be driven with two logic input signals. To produce a logic low voltage at output 32, inputs 23 and 25 are coupled together and to a logic high voltage. Thus, transistor 22A is biased off and transistor 24 is biased on, effectively shorting output 32 to ground and isolating output 32 from the supply voltage in the manner described above. To produce a logic high voltage at output 32, a logic low voltage is coupled to inputs 23 and 25, which biases on transistor 22A and biases off transistor 24.
Of the two output stages 20 and 20A shown in FIGS. 1A and 1B, output stage 20 is generally preferred. Since output stage 20 uses no P-channel transistors, the possibility of latch-up is minimized. However, in operation, the logic high voltage at the output 32 is diminished by the gate-to-source voltage required to bias on transistor 22. For example, if the input 23 is driven by a five volt signal, the VCC supply voltage is five volts, and the threshold voltage of transistor 22 is about one volt, then the output voltage at output 32 is about four volts. The output voltage can be even less of a load is coupled to output 32. The gate-to-source voltage drop of transistor 22 is usually not a problem since the minimum allowable logic high threshold of subsequent stages is less than four volts. For example, typical valid TTL logic levels are 2.4 volts for a minimum logic high threshold and 0.8 volts for a maximum logic low threshold. Therefore, as long as the power supply voltage VCC is kept at five volts, output stage 20 is capable of driving most TTL standard loads.
However, as the feature sizes of transistors shrink to enable higher levels of integration on a single integrated circuit, five volts can no longer be used as the power supply voltage. For example, gate widths of transistors used in a 4 megabit random access memory ("RAM") can be 0.6 .mu.m to 0.8 .mu.m or even less, while gate oxide can be 150 Angstroms to 200 Angstroms or less. The intensity of the electric field generated by a five volt power supply can affect the reliability of or even destroy and integrated circuit fabricated with sub-micron feature size transistors. Consequently, a lower power supply voltage such as 3.3 volts must be used to preserve the reliability and functionality of sub-micron integrated circuits.
While a lower voltage power supply solves the problem of intense electric fields, output stage 20 can no longer be used. With a 3.3 volt power supply, the voltage at the output 32 can be 2.3 volts unloaded or 2.0 volts loaded. This output voltage is not sufficient to drive a subsequent stage. The output voltage provided is within the "forbidden zone" between the allowable logic high and logic low TTL threshold levels and is therefore not a valid logic signal.
A prior method of providing a valid output voltage at the output 32 of the N-channel output stage 20 increased the voltage drive only at input 23. An output driver circuit was used to increase the voltage input above the level of the lower voltage power supply. However, such output driver circuits for increasing the voltage at input 23 typically involved complex circuitry having critical timing or delay paths.
Therefore, what is desired is a simple output driver circuit without any critical timing or delay paths for increasing the output voltage of an N-channel output stage coupled to a reduced voltage power supply.